Journals

  1. Nagothu Karmel Kranthi, Abhishek Mishra, Adil Meersha and Mayank Shrivastava, “ESD Behavior of Large Area CVD Graphene Transistors: Physical Insights and Technology Limitations”, IEEE Transactions on Electron Devices, Nov. 2018. (DOI: 10.1109/TED.2018.2877693)
  2. Milova Paul, B. Sampath Kumar, Christian Russ, Harald Gossner, Mayank Shrivastava, “Challenges & Physical Insights into the Design of Fin Based SCRs and a Novel Fin-SCR for Efficient On-Chip ESD Protection”, IEEE Transactions of Electron Devices, Volume: 65, Issue: 11, Nov. 2018. (DOI: 10.1109/TED.2018.2869630)
  3. Vipin Joshi, Shree Prakash Tiwari, and Mayank Shrivastava, “Part-I: Physical insight into breakdown voltage improvement with Carbon doping in AlGaN/GaN HEMTs”, IEEE Transactions on Electron Devices, Nov. 2018. (DOI: 10.1109/TED.2018.2878770)
  4. Vipin Joshi, Shree Prakash Tiwari, and Mayank Shrivastava,” Part II: Proposals to Independently Engineer Donor and Acceptor Trap Concentrations in GaN Buffer For Ultra High Breakdown AlGaN/GaN HEMTs”, IEEE Transactions on Electron Devices, Nov. 2018. (DOI: 10.1109/TED.2018.2878787)
  5. Sayak Dutta Gupta, Ankit Soni, Rudrarup Sengupta, Heena Khand, Bhawani Shankar, Nagboopathy Mohan, Srinivasan Raghavan, Navakanta Bhat, and Mayank Shrivastava, “Positive Threshold Voltage Shift in AlGaN/GaN HEMTs & E-mode Operation by AlxTi1-xO based Gate Stack Engineering”, to appear in IEEE Transactions of Electron Devices
  6. Bhawani Shankar, Rudrarup Sengupta, Sayak Dutta Gupta, Ankit Soni, Srinivasan Raghavan and Mayank Shrivastava, “High Current Behavior and Trap Assisted Failure Mechanisms of AlGaN/GaN Schottky Diodes Under sub-ms Transients”, to appear in IEEE Transactions of Device and Material Reliability (Invited Paper)
  7. Bhawani Shankar, Ankit Soni, Hareesh Chandrasekar, Srinivasan Raghavan and Mayank Shrivastava, “First Observations on the Trap Assisted Avalanche Instability and Safe Operating Area Concerns in AlGaN/GaN HEMTs”, to appear in IEEE Transactions of Electron Devices
  8. Bhawani Shankar and Mayank Shrivastava, “Unique ESD Behavior of AlGaN/GaN HEMTs”, to appear in IEEE Transactions on Electron Devices
  9. Bhawani Shankar and Mayank Shrivastava, “New Physical Insight into Unique Failure modes of AlGaN/GaN HEMTs under ESD Conditions”, to appear in IEEE Transactions on Device and Material Reliability
  10. Milova Paul, Christian Russ, B Sampath Kumar, Harald Gossner and Mayank Shrivastava, “Physics of Current Filamentation in ggNMOS Revisited”, IEEE Transactions on Electron Devices, Volume: 65, Issue: 7 , July 2018. (DOI: 10.1109/TED.2018.2835831)
  11. Abhishek Mishra, Adil Meersha, Srinivasan Raghavan and Mayank Shrivastava, “Observing Non-equilibrium State of Transport through Graphene Channel at the Nano-Second Time Scale”, Applied Physics Letters, Vol. 111, Issue: 26, Pages: 263101-6, Dec. 2018. (DOI: 10.1063/1.5006258)
  12. B Sampath Kumar and Mayank Shrivastava, “Part I: On the Unification of Physics of Quasi-Saturation in LDMOS Devices”, IEEE Transactions on Electron Devices, Vol. 65, Issue: 1, Pages: 191-198, Jan. 2018. (DOI:1109/TED.2017.2777004)
  13. B Sampath Kumar and Mayank Shrivastava, “Part II: RF, ESD, HCI, SOA, and Self Heating Concerns in LDMOS Devices Versus Quasi Saturation”, IEEE Transactions on Electron Devices, Vol. 65, Issue: 1, Pages: 199-206, Jan. 2018. (DOI:1109/TED.2017.2732504)
  14. Abhishek Misra, Harald Gossner and Mayank Shrivastava, “ESD Behavior of MWCNT Interconnects – Part I: Observations and Insights”, IEEE Transactions on Device and Material Reliability, Vol. 17, Issue: 4, Pages: 600-607, Dec. 2017. (DOI:1109/TDMR.2017.2756924) (Invited Review Paper)
  15. Abhishek Misra and Mayank Shrivastava, “ESD Behavior of MWCNT Interconnects – Part II: Unique Current Conduction Mechanism”, IEEE Transactions on Device and Material Reliability, Vol. 17, Issue: 4, Pages: 608-615, Dec. 2017. (DOI:1109/TDMR.2017.2738701) (Invited Review Paper)
  16. Jhnanesh Somayaji, B.Sampath Kumar, M. S. Bhat, Mayank Shrivastava, “On the Device Design Guideline, Switching/RF Performance and HCI/ESD Reliability of Non-Conventional Drain extended MOS Devices for Advanced SoC Applications”, IEEE Transactions on Electron Devices, Sep 2017
  17. Abhishek Mishra, Ravi Nandan, Srinivasan Raghavan and Mayank Shrivastava, ” Nano-second time resolved investigations on thermal implications of high-field transport through MWCNTs”, Applied Physics Letters, Vol. 110, Pages:  233111-6, May 2017. (DOI: 10.1063/1.4984282)
  18. Abhishek Mishra and Mayank Shrivastava, “Remote Joule Heating Assisted Carrier Transport in MWCNTs Probed at Nanosecond Time Scale”, Journal of Royal Society of Chemistry, Vol. 18, Pages: 28932-28938, Jun 2016. (DOI:10.1039/C6CP04497B).
  19. Mayank Shrivastava, “Drain Extended Tunnel FET – A Novel High Voltage Device for Beyond FinFET System on Chip & Automotive Applications”, IEEE Transactions on Electron Devices, Vol. 64, Issue: 2, Pages: 481 – 487, Feb. 2017. (DOI:10.1109/TED.2016.2636920)
  20. Vipin Joshi, Ankit Soni, Shree Prakash Tiwari and Mayank Shrivastava, “Computational Modeling Strategy for AlGaN/GaN HEMT Systems”, IEEE Transactions on Nanotechnology, Vol. 15, Issue: 6, Pages: 947 – 955, Nov. 2016. (DOI:1109/TNANO.2016.2615645)
  21. Kranthi Nagothu and Mayank Shrivastava, “On the ESD Behavior of Tunnel FET Devices”, IEEE Transactions on Electron Devices, Vol. 64, Issue: 1, Pages: 28 – 36, Jan. 2017. (DOI:1109/TED.2016.2630079)
  22. Kuruva Hemanjaneyulu and Mayank Shrivastava, “Fin Enabled Area Scaled Tunnel FET”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 10, Pages: 3184- 3191, Oct. 2015. (DOI:1109/TED.2015.2469678)
  23. Mayur Ghatge and Mayank Shrivastava, “Physical Insights On the Ambiguous Metal Graphene Interface and Proposal for Improved Contact Resistance”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 12, Pages: 4139- 4147, Dec 2015. (DOI:1109/TED.2015.2481507)
  24. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, Harald Gossner, and V. Ramgopal Rao, “On the Improved High-Frequency Linearity of Drain Extended MOS Devices”, IEEE Microwave and Wireless Components Letters, Vol. 26, Issue: 12, Pages: 999-1001, Dec. 2016. (DOI:10.1109/LMWC.2016.2623239)
  25. Ketankumar H. Tailor, Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, and V. Ramgopal Rao, “Part I: Physical Insights Into the Two-Stage Breakdown Characteristics of STI-Type Drain Extended PMOS Device”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 12, Pages: 4097- 4104, Dec 2015. (DOI:10.1109/TED.2015.2481899)
  26. Ketankumar H. Tailor, Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, and V. Ramgopal Rao, “Part II: Design of Well Doping Profile for Improved Breakdown and Mixed-Signal Performance of STI-Type DePMOS Device”, IEEE Transactions on Electron Devices, Vol. 62, Issue 12, Pages: 4105-4113, Dec 2015. (DOI:10.1109/TED.2015.2488683)
  27. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “Part II: A Fully Integrated RF PA in 28nm CMOS with Device Design for Optimized Performance and ESD Robustness”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 10, Pages: 3176-3183, Oct. 2015. (DOI:10.1109/TED.2015.2470109)
  28. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “Part I: High Voltage MOS Device Design for Improved Static and RF Performance”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 10, Pages: 3168- 3175, Oct. 2015. (DOI:10.1109/TED.2015.2470117)
  29. Peeyusha S. Swain, Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner and V. Ramgopal Rao, “On the Geometrically Dependent Quasi-Saturation and gm Reduction in Advanced DeMOS Transistors”, IEEE Transactions on Electron Devices, Vol. 63, Issue: 4, Pages: 1621 1629, April 2016. (DOI:10.1109/TED.2016.2528282)
  30. Mayank Shrivastava, Neha Kulshrestha and Harald Gossner, “ESD Investigations of Multiwalled Carbon Nanotubes”, IEEE Transactions on Device and Material Reliability, Vol. 14, Issue: 1, Pages: 555 – 563, March, 2014. (DOI:10.1109/TDMR.2013.2288362)
  31. Peeyush Swain, Mayank Shrivastava, Harald Gossner, M. S. Baghini and V. Ramgopal Rao, “Device–Circuit Co-design for Beyond 1 GHz 5 V Level Shifter Using DeMOS Transistors”, IEEE Transactions on Electron Devices, Vol. 60, Issue: 11, Pages: 3827-3834, November, 2013. (DOI:10.1109/TED.2013.2283421)
  32. Anukool Rajoriya, Mayank Shrivastava, Harald Gossner, Thomas Schulz and V. Ramgopal Rao “Sub 0.5V Operation of Performance Driven Mobile Systems Based on Area Scaled Tunnel FET Devices”, IEEE Transactions on Electron Devices, Vol. 60, Issue: 8, Pages: 2626-2633, August, 2013. (DOI:10.1109/TED.2013.2270566)
  33. Mayank Shrivastava and Harald Gossner, “A Review on the ESD Reliability of Drain Extended MOS Devices”, IEEE Transactions on Device and Material Reliability, Vol. 12, Issue: 4, Pages: 615-625, December, 2012. (DOI:10.1109/TDMR.2012.2220358) (Invited Review Paper)
  34. Mayank Shrivastava, Harald Gossner and V. Ramgopal Rao, “A Novel Drain Extended FinFET Device for High Voltage High Speed Applications”, IEEE Electron Device Letters, Vol. 33, Issue: 10, Pages: 1432-1434, October, 2012. (DOI:10.1109/LED.2012.2206791)
  35. Mayank Shrivastava, Harald Gossner and Christian Russ, “A Novel Drain Extended NMOS Device with Spreading Filament under ESD Stress”, IEEE Electron Device Letters, Vol. 33, Issue: 9, Pages: 1294-1296,  September, 2012. (DOI:10.1109/LED.2012.2205553)
  36. Mayank Shrivastava, Manish Agrawal, Sunny Mahajan, Harald Gossner, Thomas Schulz, Dinesh Kumar Sharma, and V. Ramgopal Rao, “Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures”, IEEE Transactions on Electron Devices, Vol. 59, Issue: 5, Pages:1353-1363, May, 2012. (DOI:10.1109/TED.2012.2188296)
  37. Mayank Shrivastava, Ruchit Mehta, Shashank Gupta, M. Shojaei Baghini, D. K. Sharma, Harald Gossner, T. Schulz, K. Arnim, W. Molzer, V. Ramgopal Rao, “Towards System On Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines”, IEEE Transactions on Electron Devices, Vol. 58, Issue: 6, Pages: 1597-1607, June, 2011. (DOI:10.1109/TED.2011.2123100) (This paper is recognized as feature article in Synopsys newsletter, May 2011)
  38. Ram Asra, Mayank Shrivastava, K. V. R. M. Murali, R. K. Pandey, Harald Gossner and V. Ramgopal Rao, “A Tunnel FET for VDD Scaling Below 0.6 V With a CMOS-Comparable Performance”, IEEE Transactions on Electron Devices, Vol. 58, Issue: 7, Pages: 1855-1863, July, 2011. (DOI:10.1109/TED.2011.2140322)
  39. Rajesh A. Thakker, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh K. Sharma, V. Ramgopal Rao, and Mahesh B. Patil, ” A Novel Architecture for Improving Slew Rate in FinFET-based Op-Amps and OTAs”, Microelectronics Journals, Vol. 42, Issue: 5, Pages: 758–765, May, 2011. (https://doi.org/10.1016/j.mejo.2011.01.010)
  40. Mayank Shrivastava, Ruchil Jain, M. Shojaei Baghini, Harald Gossner and V. Ramgopal Rao, “Solution towards the OFF state degradation in Drain extended MOS device”, IEEE Transactions on Electron Devices, Vol. 57, Issue: 12, Pages:  3536-3539, December, 2010. (DOI:10.1109/TED.2010.2082549)
  41. Amitabh Chatterjee, Mayank Shrivastava, Harald Gossner, Sameer Pendharkar, Forrest Brewer, Charvaka Duvvury, ” An Insight Into the ESD Behavior of the Nanometer-Scale Drain-Extended NMOS Device—Part I: Turn-On Behavior of the Parasitic Bipolar”, IEEE Transactions on Electron Devices, Vol. 58, Issue: 2, Pages: 309 – 317, February, 2011. (DOI:10.1109/TED.2010.2093010)
  42. Amitabh Chatterjee, Mayank Shrivastava, Harald Gossner, Sameer Pendharkar, Forrest Brewer, Charvaka Duvvury, ” An Insight Into ESD Behavior of Nanometer-Scale Drain Extended NMOS (DeNMOS) Devices: Part II(Two-Dimensional Study-Biasing & Comparison With NMOS)”, IEEE Transactions on Electron Devices, Vol. 58, No. 2, Pages: 318 – 326, February, 2011. (DOI:10.1109/TED.2010.2093011)
  43. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, “Part I: On the Behavior of STI-Type DeNMOS Device under ESD Conditions”, IEEE Transactions on Electron Devices, Vol. 57, Issue: 9, Pages: 2235 – 2242, September 2010. (DOI:10.1109/TED.2010.2055276)
  44. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, “Part II: On the Three-Dimensional Filamentation and Failure Modeling of STI Type DeNMOS Device Under Various ESD Conditions”, IEEE Transactions on Electron Devices, Vol. 57, Issue: 9, Pages: 2243 – 2250, September 2010. (DOI:10.1109/TED.2010.2055278)
  45. Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, “A novel bottom spacer FinFET structure for improved power-delay & short channel performance”, IEEE Transactions on Electron Devices, Vol. 57, Issue: 6, Pages: 1287-1994, June 2010. (DOI:10.1109/TED.2010.2045686)
  46. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “PART I-“Mixed Signal Performance of Various High Voltage Drain Extended MOS devices” IEEE Transactions on Electron Devices, Vol. 57, Issue: 2, Pages: 448-457, Feb 2010. (DOI:10.1109/TED.2009.2036796)
  47. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “PART II-“A Novel scheme to optimize the mixed signal performance and hot carrier reliability of Drain Extended MOS devices” IEEE Transactions on Electron Devices, Vol. 57, Issue: 2, Pages: 458-465, Feb 2010. (DOI:10.1109/TED.2009.2036799)
  48. Mayank Shrivastava, Maryam Shojaei Baghini, A. Sachid, Dinesh Kumar Sharma, V. Ramgopal Rao, “A Novel and Robust Approach for Common Mode Feedback using IDDG FinFET”, IEEE Transactions on Electron Devices, Volume: 55, Issue: 11, Pages: 3274-3282, Nov 2008. (DOI:10.1109/TED.2008.2004475)

Peer Reviewed Conferences

  1. Nagothu Karmel Kranthi, Akram Salman, Gianluca Boselli and Mayank Shrivastava, “Current Filament Dynamics Under ESD Stress in High Voltage (Bidirectional) SCRs and Its Implications on Power Law Behavior”, to appear in 57th IEEE International Reliability Physics Symposium (IRPS), Monterey, California, USA, March 31 – April 4, 2019
  2. Abhishek Mishra, Adil Meersha, N. K. Kranthi, Kruti Trivedi, Harsha B. Variar, Veena Bellamkonda, Srinivasan Raghavan and Mayank Shrivastava, “First Demonstration and Physical Insights into Time-dependent Breakdown of Graphene Channel and Interconnects”, to appear in 57th IEEE International Reliability Physics Symposium (IRPS), Monterey, California, USA, March 31 – April 4, 2019
  3. Sayak Dutta Gupta, Vipin Joshi, B. Shankar, S. Shikha, Srinivasan Raghavan and Mayank Shrivastava, “UV-Assisted Probing of Deep-Level Interface Traps in GaN MISHEMTS and Its Role In Threshold Voltage & Gate Leakage Instabilities”, to appear in 57th IEEE International Reliability Physics Symposium (IRPS), Monterey, California, USA, March 31 – April 4, 2019
  4. Nagothu Karmel Kranthi, B. Sampath Kumar, Akram Salman, Gianluca Boselli and Mayank Shrivastava, “Physical Insights into the Low Current ESD Failure of LDMOS-SCR and Its Implication on Power Scalability”, to appear in 57th IEEE International Reliability Physics Symposium (IRPS), Monterey, California, USA, March 31 – April 4, 2019
  5. Bhawani Shankar, Ankit Soni, Sayak Dutta Gupta, Swati Shikha, Sandeep Singh, Srinivasan Raghavan and Mayank Shrivastava, “Time Dependent Early Breakdown of AlGaN/GaN Epi Stacks and Shift in SOA Boundary of HEMTs Under Fast Cyclic Transient Stress”, 64th IEEE International Electron Device Meeting (IEDM)– 2018, CA, USA
  6. Bhawani Shankar, A. Soni, S. D. Gupta, R. Sengupta, H. Khand, N. Mohan, S. Raghavan, N. Bhat and M. Shrivastava, ‘Design and Reliability of GaN Power HEMT Technology (Invited)’, ECS Meeting Abstracts, vol. MA2018-02, no. 16, p. 713, 2018. [Online]. Available: http : / / ma . ecsdl . org / content / MA2018 – 02/16/713.abstract
  7. B Sampath Kumar, Milova Paul, Harald Gossner and Mayank Shrivastava, “Physical Insights into the ESD Behavior of Drain extended FinFETs”, 40th EOSESD Symposium, Sep. 23rd to 28th 2018, Reno, NV, USA
  8. Bhawani Shankar, R. Singh, R. Sengupta, H. Khand, A. Soni, S. D. Gupta, S. Raghavan, H. Gossner and M. Shrivastava, ‘Trap Assisted Stress Induced ESD Reliability of GaN Schottky Diodes’, in 2018 40th ElectricalOverstress/Electrostatic Discharge Symposium (EOS/ESD), 2018, pp. 1–6. (DOI: 10.23919/EOS/ESD.2018.8509745).
  9. S. Kumar, M. Paul, H. Gossner and M. Shrivastava, “Performance and reliability insights of drain ex- tended FinFET devices for high voltage SoC applications”. IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Chicago, IL, 2018, pp. 72-75.
  10. Bhawani Shankar, A. Soni, S. D. Gupta, R. Sengupta, H. Khand, N. Mohan, S. Raghavan and M. Shrivast- ava, ‘On the Trap Assisted Stress Induced Safe Operating Area Limits of AlGaN/GaN HEMTs’, in 2018 IEEE International Reliability Physics Symposium (IRPS), 2018, 4E.4–1–4E.4–5. (DOI: 10.1109/IRPS.2018.8353596).
  11. Bhawani Shankar, A. Soni, S. D. Gupta and M. Shrivastava, ‘Safe Operating Area (SOA) Reliability of Po- larization Super Junction (PSJ) GaN FETs’, in 2018 IEEE International Reliability Physics Symposium (IRPS), 2018, 4E.3–1–4E.3–4. (DOI: 10.1109/IRPS.2018.8353595).
  12. Paul, B. S. Kumar, H. Gossner and M. Shrivastava, “Contact and junction engineering in bulk FinFET technology for improved ESD/latch-up performance with design trade-offs and its implications on hot carrier reliability”. IEEE International Reliability Physics Symposium (IRPS), Burlingame, CA, 2018, pp. 3E.3- 1-3E.3-6.
  13. K. Kranthi, A. Mishra, A. Meersha, H. B. Variar and M. Shrivastava, “Defect-Assisted Safe Operating Area Limits and High Current Failure in Graphene FETs,” 2018 IEEE International Reliability Physics Symposium (IRPS), Burlingame, CA, 2018, pp. 3E.1-1-3E.1-5.
  14. Sinha, P. Bhattacharya, S. Sambandan and M. Shrivastava, “On the ESD behavior of a-Si:H based thin film transistors: Physical insights, design and technological implications,” 2018 IEEE International Reliability Physics Symposium (IRPS), Burlingame, CA, 2018, pp. 3E.2-1-3E.2-6
  15. Karmel Kranthi Nagothu, Abhishek Mishra, Adil Meersha and Mayank Shrivastava, “On the ESD Reliability issues in Carbon electronics: Graphene and Carbon Nano Tubes”, 31st International Conference on VLSI Design (VLSID), Jan 2018. (DOI: 1109/VLSID.2018.117)
  16. Milova Paul, B. Sampath Kumar, Christian Russ, Harald Gossner, Mayank Shrivastava, “FinFET SCR: Design Challenges and Novel Fin SCR Approaches for On-Chip ESD Protection”, Proceedings of EOSESD Symposium, September 2017, Sep. 12th – Sep. 15th, USA. (DOI: 23919/EOSESD.2017.8073437)
  17. Bhawani Shankar, Rudrarup Sengupta, Sayak Dutta Gupta, Ankit Soni, Nagaboopathy Mohan, Navakant Bhat, Srinivasan Raghavan and Mayank Shrivastava1, “On the ESD Behavior of AlGaN/GaN Schottky Diodes and Trap Assisted Failure Mechanism”, Proceedings of EOSESD Symposium, September 2017, Sep. 12th – Sep. 15th, USA. (DOI: 23919/EOSESD.2017.8073423)
  18. Rajat Sinha, N.K. Kranthi, Sanjiv Sambandan and Mayank Shrivastava, “On the ESD Behavior of Pentacene Channel Organic Thin Film Transistor”, Proceedings of EOSESD Symposium, September 2017, Sep. 12th – Sep. 15th, USA. (DOI: 23919/EOSESD.2017.8073426)
  19. Vipin Joshi, Bhawani Shankar, Shree Prakash Tiwari and Mayank Shrivastava, “Dependence of Avalanche Breakdown on Surface & Buffer Traps in AlGaN/GaN HEMTs”, 22nd IEEE SISPAD, Japan, September 7-9, 2017. (DOI: 23919/SISPAD.2017.8085276)
  20. Sampath Kumar, Milova Paul and Mayank Shrivastava, “On the Design Challenges of Drain Extended FinFETs for Advance SoC Integration”, 22nd IEEE SISPAD, Japan, September 7-9, 2017. (DOI: 10.23919/SISPAD.2017.8085296)
  21. K. Kranthi, Abhishek Mishra, Adil Meersha and Mayank Shrivastava, “ESD Behavior of Large Area CVD Graphene RF Transistors: Physical Insights and Technology Implications”, Proceedings of IEEE International Reliability Physics Symposium, USA, April 4th – April 6th, 2017. (DOI: 10.1109/IRPS.2017.7936298)
  22. Bhawani Shankar, Mayank Shrivastava, “Trap Assisted Avalanche Instability and Safe Operating Area Concerns in AlGaN/GaN HEMTs”, Proceedings of IEEE International Reliability Physics Symposium, USA, April 4th – April 6th, 2017. (DOI: 1109/IRPS.2017.7936414)
  23. Milova Paul, Christian Russ, B Sampath Kumar, Harald Gossner and Mayank Shrivastava, “Physics of Current Filamentation in ggNMOS Revisited: Was Our Understanding Scientifically Complete?”, Proceedings of IEEE VLSI Design Conference, Jan. 8th – 11th, 2017 (Received outstanding research paper award) (DOI: 1109/VLSID.2017.32)
  24. Bhawani Shankar and Mayank Shrivastava, “ESD Behavior of AlGaN/GaN HEMT on Si: Physical Insights, Design Aspects, Cumulative Degradation and Failure Analysis”, Proceedings of IEEE VLSI Design Conference, Jan. 8th – 11th, 2017. (DOI: 1109/VLSID.2017.57)
  25. Adil Meersha, Sathyajit B and Mayank Shrivastava, “A Systematic Study on the Hysteresis Behavior and Reliability of MoS2 FET”, Proceedings of IEEE VLSI Design Conference, Jan. 8th – 11th, 2017. (DOI: 1109/VLSID.2017.67)
  26. Adil Meersha, Harsha B Variar, Krishna Bharadwaj, Abhishek Mishra, Srinivasan Raghavan, Navakanta Bhat and Mayank Shrivastava, “Record Low Metal – (CVD) Graphene Contact Resistance Using Atomic Orbital Overlap Engineering”, Proceedings of IEEE International Electron Device Meeting, Dec. 5th – Dec. 7th, San Francisco, CA, USA, 2016. (DOI: 1109/IEDM.2016.7838352)
  27. Abhishek Mishra and Mayank Shrivastava, “Unique Current Conduction Mechanism through Multi Wall CNT Interconnects under ESD Conditions”, Proceedings of EOSESD Symposium, Anaheim, CA, USA, 11th – 14th September, 2016. (DOI: 1109/EOSESD.2016.7592528)
  28. Peeyusha S. Swain, Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner and V. Ramgopal Rao, “Device-Circuit Co-design for High Performance Level Shifter by Limiting Quasi-saturation Effects in Advanced DeMOS Transistors”, IEEE INEC, 9th – 11th, May, 2016, China. DOI: 10.1109/INEC.2016.7589264
  29. Abhishek Mishra and Mayank Shrivastava, “New Insights on the ESD Behavior and Failure Mechanism of Multi Wall CNTs”, Proceedings of IEEE International Reliability Physics Symposium, Pasadena, CA, USA, 17th – 19th April, 2016. DOI: 10.1109/IRPS.2016.7574609
  30. Bhawani Shankar and Mayank Shrivastava, “Unique ESD Behavior and Failure Modes of AlGaN/GaN HEMTs”, Proceedings of IEEE International Reliability Physics Symposium, Pasadena, CA, USA, 17th – 19th April, 2016. DOI: 10.1109/IRPS.2016.7574608
  31. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “A Fully-Integrated Radio-Frequency Power Amplifier in 28nm CMOS Technology mounted in BGA Package”, Proceedings of IEEE VLSI Design Conference, Jan. 2016. DOI: 10.1109/VLSID.2016.30
  32. Ketankumar Tailor, Mayank Shrivastava, Harald Gossner, Maryam Baghini, Ramgopal Rao, “On the Breakdown Physics of Trench-Gate Drain Extended NMOS”, Proceedings of IEEE Electron Devices and Solid-State Circuits Conference, June 2015, Singapore. DOI: 10.1109/EDSSC.2015.7285240
  33. Ketankumar Tailor, Mayank Shrivastava, Harald Gossner, Maryam Baghini, Ramgopal Rao, “Comparison of Breakdown Characteristics of DeNMOS Devices with Various Drain Structures”, Proceedings of IEEE Electron Devices and Solid-State Circuits Conference, June 2015, Singapore. DOI: 10.1109/EDSSC.2015.7285222
  34. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “Drain Extended MOS Device Design for Integrated RF PA in 28nm CMOS with Excellent FoM and ESD Robustness”, Proceeding of IEEE International Electron Device Meeting (IEDM) Dec. 2014, San Francisco, CA, USA. DOI: 10.1109/IEDM.2014.7046974
  35. Mayank Shrivastava and Harald Gossner, “ESD Behavior of Metallic Carbon Nanotubes”, Proceedings of 36th EOSESD Symposium, 7th – 12th Sep. 2014, Tucson, Arizona, USA. INSPEC Accession Number: 14789864
  36. Mayank Shrivastava, Christian Russ, Harald Gossner, S. Bychikhin, D. Pogany and E. Gornik, “ESD Robust DeMOS Devices in Advanced CMOS Technologies”, Proceedings of EOSESD symposium, 11th – 15th Sep. 2011, Anaheim, California, USA. Electronic ISBN: 978-1-58537-193-8
  37. Junjun Li, Rahul Mishra, Mayank Shrivastava, Yang Yang, Robert Gauthier, Christian Russ, “Technology Scaling Effects of Silicide-blocked PMOSFET Devices under ESD like conditions in Advanced Nanometer Node Bulk CMOS Technologies”, Proceedings of EOSESD Symposium, 11-15 Sep. 2011, Anaheim, California, USA. INSPEC Accession Number: 12316385
  38. Mayank Shrivastava, Manish Agrawal, Jasmin Aghassi, Harald Gossner, Wolfgang Molzer, Thomas Schulz, V. Ramgopal Rao, “On the thermal failure in nanoscale devices: Insight towards Heat Transport and Design Guidelines for Robust Thermal Management & EOS/ESD Reliability”, Proceedings of IEEE International Reliability Physics Symposium, 10-14 April, 2011, Monterey, CA, USA. DOI: 10.1109/IRPS.2011.5784498
  39. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini and V. Ramgopal Rao, “On the Transient Behavior of Various Drain Extended MOS Devices under the ESD stress conditions”, Proceedings of 7th International SoC Design Conference (ISOCC 2010), November 22-23, 2010, Songdo Convensia, Incheon, Korea (Invited). DOI: 10.1109/SOCDC.2010.5682922
  40. Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “On the failure mechanism and current instabilities in RESURF type DeNMOS device under ESD conditions”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), May 2nd – 6th, 2010, Anaheim, California, USA. DOI: 10.1109/IRPS.2010.5488723
  41. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini and V. Ramgopal Rao, “3D TCAD based approach for the Evaluation of Nanoscale Devices during ESD Failure”, Proceedings of 7th International SoC Design Conference (ISOCC 2010), November 22-23, 2010, Songdo Convensia, Incheon, Korea (Invited). DOI: 10.1109/SOCDC.2010.5682919
  42. Mayank Shrivastava, S. Bychikhin, D. Pogany, Jens Schneider, M. Shojaei Baghini, Harald Gossner, Erich Gornik, V. Ramgopal Rao, “On the differences between 3D filamentation and failure of n & p type drain extended MOS devices under ESD condition”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), May 2nd – 6th, 2010, Anaheim, California, USA. DOI: 10.1109/IRPS.2010.5488785
  43. Mayank Shrivastava, Bhaskar Verma, M. Shojaei Baghini, Christian Russ, Dinesh K. Sharma, Harald Gossner, V. Ramgopal Rao, “Benchmarking the Device Performance at sub 22 nm node Technologies using an SoC Framework”, Proceedings of IEEE International Electron Device Meeting (IEDM), 7th -9th Dec, 2009, Baltimore, USA. DOI: 10.1109/IEDM.2009.5424311
  44. Mayank Shrivastava, S. Bychikhin, D. Pogany, Jens Schneider, M. Shojaei Baghini, Harald Gossner, Erich Gornik, V. Ramgopal Rao, “Filament Study of STI type Drain extended NMOS device using Transient Interferometric Mapping”, Proceedings of IEEE International Electron Device Meeting (IEDM), 7th -9th Dec, 2009, Baltimore, USA. DOI: 10.1109/IEDM.2009.5424337
  45. Mayank Shrivastava, Jens Schneider, Ruchil Jain, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “IGBT plugged in SCR device for ESD protection in advanced CMOS technology”, Proceedings of EOS/ESD symposium, August 30th – September 4th, 2009, Anaheim, CA, USA. CD-ROM ISBN: 978-1-58537-176-1
  46. Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “Highly resistive body STI: n-DEMOS: An optimized DEMOS device to achieve moving current filaments for robust ESD protection”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), April 26th – 30th, 2009, Montreal, Quebec, Canada. DOI: 10.1109/IRPS.2009.5173344
  47. Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “A New Physical Insight and 3D Device Modeling of STI Type DENMOS Device Failure under ESD Conditions”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), April 26th – 30th, 2009, Montreal, Quebec, Canada. DOI: 10.1109/IRPS.2009.5173327
  48. A. B. Sachid, Mayank Shrivastava, R. A. Thakkar, M. Shojaei Baghini, D. K. Sharma, M. B. Patil, V. Ramgopal Rao, “Technology-Aware Design (TAD) for Sub-45nm CMOS Technologies”, Intel Asia Academic Forum 2008, Oct. 20th – Oct. 22nd 2008, Taipei, Taiwan. (Received the best research paper award).
  49. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, “Reliability aware I/O design for sub 45nm node CMOS technology”, IWPSD-2009, 15th -19th Dec, 2009 (Invited).
  50. Saurabh Nema, Mayank Shrivastava, Angada B. Sachid, A. K. Saxena, Anand Bulusu, “A Novel Scaling Strategy for Underlap FinFETs”, ICCCD, India, 2010.
  51. Mayank Shrivastava, Christian Russ, Harald Gossner, “On the Impact of ESD Implant and Filament Spreading in Drain extended NMOS devices”, International ESD Workshop, May 2011, Lake Tahoe, CA, USA.

Patents (Granted/Issued)

  1. Milova Paul, Mayank Shrivastava, Sampath Kumar, Christian Russ and Harald Gossner, “Dual Fin Silicon Controlled Rectifier (SCR) Electrostatic Discharge (ESD) Protection Device”, US Patent Pending, Application No: 15/883,306, Filed on: 30-Jan-18 (Indian Patent, Application No 201741003771, Filed on 1st Feb. 2017)
  2. Mayank Shrivastava, Milova Paul, Christian Russ and Harald Gossner, “Non-planar Electrostatic Discharge (ESD) Protection Devices With Nano Heat Sinks”, US Patent Pending, Application No: 15/883,749, Filed on: 30-Jan-18 (Indian Patent, Application No 201741003773, Filed on 1st Feb. 2017)
  3. Mayank Shrivastava, Milova Paul, Christian Russ and Harald Gossner, “Low Trigger And Holding Voltage Silicon Controlled Rectifier (SCR) For Non-Planar Technologies”, US Patent Pending, Application No: 15/883,591, Filed on: 01-Feb-18 (Indian Patent, Application No 201741003772, Filed on 1st Feb. 2017)
  4. Mayank Shrivastava, Milova Paul and Harald Gossner, “FinFET SCR With SCR Implant Under Anode And Cathode Junctions”, US Patent Pending, Application No: 15/899,102, Filed on: 19-Feb-18 (Indian Patent, Application No 201741006746, Filed on 25th Feb. 2017)
  5. Mayank Shrivastava, Milova Paul and Harald Gossner, “Electrostatic Discharge (ESD) Protection Devices For ESD Robustness And Latch-Up Immunity”, US Patent Pending, Application No: 15/899,117, Filed on: 19-Feb-18 (Indian Patent, Application No 201741006745, Filed on 25th Feb. 2017)
  6. Mayank Shrivastava, Christian Russ and Harald Gossner, “Tunable FIN-SCR for Robust ESD Protection”, United States Patent (2017) 9,608,098.
  7. Mayank Shrivastava and Christian Russ, “Semiconductor devices and arrangements including dummy gates for electrostatic discharge protection”, United States Patent (2017) 9,595,516.
  8. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, “Drain extended field effect transistors and methods of formation thereof”, United States Patent (2017) 9,647,069.
  9. Mayank Shrivastava, “Drain extended Tunnel FET”, US Patent Pending, Application No: 15/439,951, Filed on: 23-Feb-17 (Indian Patent Application No: 201641006497, Filed on Feb 26th 2016.)
  10. Mayank Shrivastava and Christian Russ, “Semiconductor devices and arrangements for electrostatic (ESD) protection”, United States Patent (2016) 9,356,013
  11. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, Ramgopal Rao, “Methods for manufacturing a semiconductor device”, United States Patent (2016) 9,368,573
  12. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-effect device and manufacturing method thereof”, United States Patent (2016) 9,401,352
  13. Mayank Shrivastava, Maryam Shojaei Baghini, Christian Russ, Harald Gossner, Ramgopal Rao, “High voltage semiconductor devices”, United States Patent (2016) 9,455,275
  14. Mayank Shrivastava and Harald Gossner, “Silicon controlled rectifier (SCR) device for bulk FinFET technology”, United States Patent (2015) 8,785,968
  15. Mayank Shrivastava, Christian Russ and Harald Gossner, “Tunable Fin-SCR for Robust ESD Protection”, United States Patent (2015) 8,963,201
  16. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-Effect Device and Manufacturing Method Thereof”, United States Patent (2015) 9,035,375
  17. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, “Drain Extended Field Effect Transistors and Methods of Formation Thereof”, United States Patent (2015) 9,087,892
  18. Mayank Shrivastava and Christian Russ, “FinFET and Fin-BJT SCR as ESD clamp with Built-In trigger circuit and Current Ballasting mechanism including Checker-Board Layout Technique for Uniform SCR Turn-On”, United States Patent (2015) 20150008476.
  19. Christian Russ, Mayank Shrivastava and Markus Schwiegershausen, “Transient-Triggered SCR for FinFET Technology (FF-TTSCR) for ESD Protection of RF IO”, United States Patent pending (Filed August 2015).
  20. Mayank Shrivastava and Harald Gossner, “Drain extended MOS device for Bulk FinFET technology”, United States Patent (2014) 8,629,420
  21. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Semiconductor devices and methods for manufacturing a semiconductor device”, United States Patent (2014) 8,643,090
  22. Mayank Shrivastava, Christian Russ, Harald Gossner, “Low voltage ESD clamping using high voltage devices”, United States Patent (2014) 8,654,491
  23. Mayank Shrivastava, Maryam Shojaei Baghini, Christian Russ, Harald Gossner, Ramgopal Rao, “High voltage semiconductor devices”, United States Patent (2014) 8,664,720
  24. Mayank Shrivastava, Christian Russ, Harald Gossner, “Selective current pumping to enhance low-voltage ESD clamping using high voltage devices”, United States Patent (2014) 8,681,461
  25. Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, “Nonvolatile floating gate analog memory cell”, United States Patent (2013) 8,436,413
  26. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-effect device and manufacturing method thereof”, United States Patent (2013) 8,354,710
  27. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, Ramgopal Rao, Christian Russ, “Device and method for coupling first and second device portions”, United States Patent (2013) 8,455,947
  28. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, “Drain extended field effect transistors and methods of formation thereof”, United States Patent (2013) 8,536,648
  29. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei,” Semiconductor devices with trench isolations”, United States Patent (2012) 8,097,930
  30. Rajesh Thakkar, Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, M. B. Patil, “Operational Amplifier Having Improved Slew Rate ” United States Patent (2012) 8,089,314

Patents (Pending)

  1. Mayank Shrivastava and Vipin Joshi, “Doping And Trap Profile Engineering In Gan Buffer To Maximize Algan/GaN Hemt Epi Stack Breakdown Voltage”, Indian Patent Application 201841020899, Filed on June 5th 2019
  2. Mayank Shrivastava, “GaN HEMT device with improved gate control and higher breakdown voltage”, Indian patent Application
  3. Ansh, Hemanjaneyulu Kuruva and Mayank Shrivastava, “Methods Of Manufacturing 2-Dimentional Semiconductor Transistors”, Indian Patent Application 201741033081, September, 2017
  4. Mayank Shrivastava, Sayak Dutta Gupta, Ankit Soni and Srinivasan Raghavan, “e-Mode Field Effect High Electron Mobility (HEMT) Transistor”, Indian Patent Application 201741030570, August 2017
  5. S. Kranthi, K. Hemanjaneyulu, and Mayank Shrivastava, “ESD Robust Tunnel FET Device”, Indian Patent Application 201741025123, July 2017
  6. Rohit Soman, Ankit Soni, Mayank Shrivastava, S. Raghavan and Navakanta Bhat “GaN HEMT Device with high Breakdown Voltage”, Indian Patent Application, May 2017
  7. Mayank Shrivastava, “Recess Gate Superjunction High-electron-mobility transistor (HEMT)”, Indian Patent Application 201741024695, July 2017.
  8. Mayank Shrivastava and Kuruva Hemanjaneyulu “Fin enabled area scaled tunnel field Effect transistor”, Patent Application No: 2625/CHE/2015, Filed on May 26th 2015.
  9. Mayank Shrivastava, “Miniaturized, High Power Density Power Electronic System on a Chip”, Patent Application No: 1355/CHE/2015, Filed on March 19th 2015.
  10. Rajesh Thakkar, Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, M. B. Patil, ” A Novel Architecture for Improving Slew Rate in FinFET-based Op-Amps and OTAs”, Patent Application No 542/MUM/2010, Filed on 2nd March 2010.
  11. Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, “Independently Driven Double Gate (IDDG) Nonvolatile floating gate analog memory cell”, Indian Patent pending, 2008, Patent Application No 2217/MUM/2008, Filed on 15th October 2008.

Books, Book chapters and Technical Briefs

  1. Chapter titled “Towards Drain extended FinFETs for SoC applications” in book “Toward Quantum FinFET”, edited by Weihua Han and Zhiming M. Wang, Springer, Dec. 2013, ISBN 978-3-319-02021-1.
  2. Mayank Shrivastava and V. Ramgopal Rao, “Tunnel Field Effect Transistors”, Present, Past and Future, Technical Brief appeared in the IEEE EDS Newsletters, July 2016 (Cover page article).